Alif Semiconductor /AE302F80C1557LE_CM55_HP_View /OSPI0 /OSPI_SR

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Interpret as OSPI_SR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Val_0x0)BUSY 0 (Val_0x0)TFNF 0 (Val_0x0)TFE 0 (Val_0x0)RFNE 0 (Val_0x0)RFF 0CMPLTD_DF

BUSY=Val_0x0, RFF=Val_0x0, RFNE=Val_0x0, TFE=Val_0x0, TFNF=Val_0x0

Description

OSPI Status Register

Fields

BUSY

OSPI Busy Flag. When set, indicates that a serial transfer is in progress; when cleared indicates that the OSPI is idle or disabled.

0 (Val_0x0): OSPI is idle or disabled.

1 (Val_0x1): OSPI is actively transferring data.

TFNF

Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full.

0 (Val_0x0): Transmit FIFO is full.

1 (Val_0x1): Transmit FIFO is not full.

TFE

Transmit FIFO Empty. When the transmit FIFO is completely empty, this bit is set. When the transmit FIFO contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt.

0 (Val_0x0): Transmit FIFO is not empty.

1 (Val_0x1): Transmit FIFO is empty.

RFNE

Receive FIFO Not Empty. Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty. This bit can be polled by software to completely empty the receive FIFO.

0 (Val_0x0): Receive FIFO is empty.

1 (Val_0x1): Receive FIFO is not empty.

RFF

Receive FIFO Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared.

0 (Val_0x0): Receive FIFO is not full.

1 (Val_0x1): Receive FIFO is full.

CMPLTD_DF

Completed Data Frames. This bit field indicates total data frames transferred in the previous internal DMA transfer.

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